1. Field of the Invention
The present invention relates to a synchronization circuit which synchronizes an asynchronous signal.
2. Description of the Related Art
In recent years, various devices have been required to perform processes at a high speed with less power consumption. Therefore, each module in the device is designed to operate at each optimal speed. Because of this, system clocks of the modules in the device are sometimes asynchronous to each other. When data are sent and received between the modules having system clocks that are asynchronous to each other, a synchronization circuit to synchronize the system clock and input signals is required in the module which receives the input signals.
FIG. 1 is a diagram showing an example of a circuit configuration of a conventional synchronization circuit. A synchronization circuit 10 shown in FIG. 1 is provided in a module which receives data when sending and receiving data between modules. In the synchronization circuit 10, an input signal AD is latched into flip-flop circuits 11 and 12 by a system clock SCK to be synchronized with the system clock SCK.
In the flip-flop circuits 11 and 12, when a rising edge of the system clock SCK is a reference edge, there are a set-up time ts before the reference edge, during which the input signal AD has to be stabilized and a hold time th after the reference edge, during which the input signal AD has to be held. The flip-flop circuits 11 and 12 can properly read in the input signal AD when the stable input signal AD is inputted in the set-up time ts and the input signal AD is held during the hold time th.
For example, when a signal level of the input signal AD inputted from a data input terminal D is not stabilized in the set-up and hold time (ts+th) in the flip-flop circuit 11, an output signal PD of the flip-flop circuit 11 becomes metastable. A metastable state is an unstable state that the output signal is neither at a high level (hereinafter H-level) or a low level (hereinafter L-level). Then, the output signal of the flip-flop circuit 11 is converged to one of the H-level and the L-level. After the metastable state, the output signal is converged to one of the levels completely randomly, regardless of the level of the input signal AD. Therefore, due to the metastable state generated in the flip-flop circuit 11 of a preceding stage, the input signal may not be properly sent to the flip-flop circuit 12 of a subsequent stage.
In view of this, there is disclosed a circuit configuration to properly transmit an input signal even when a metastable state occurs. FIG. 2 shows another example of a circuit configuration of a conventional synchronization circuit.
A synchronization circuit 20 shown in FIG. 2 includes flip-flop circuits 21, 22, and 23, a selection circuit 24, and a logic circuit 25. The flip-flop circuits 21 and 22 operate in synchronization with signals having an opposite phase to each other. The flip-flop circuit 21 operates in synchronization with a system clock SCK while the flip-flop circuit 22 operates in synchronization with an inverted signal of the system clock SCK.
In the synchronization circuit 20, an output signal SYNC1 of the flip-flop circuit 21 of a preceding stage and an output signal SYNC3 of the flip-flop circuit 23 of a subsequent stage to be an output signal of the synchronization circuit 20 are compared to detect whether a metastable state has occurred. Based on the comparison result, one of the output signal SYNC1 of the flip-flop circuit 21 and an output signal SYNC2 of the flip-flop circuit 22 is selected and inputted to the flip-flop circuit 23.
An equivalent circuit configuration to the synchronization circuit shown in FIG. 2 is disclosed in, for example, Patent Document 1.
[Patent Document 1] Japanese Patent Application Publication No. 7-13927
With the synchronization circuit disclosed in Patent Document 1, however, the input signal and the output signal of the flip-flop circuit of the subsequent stage are compared to detect an occurrence of a metastable state. Therefore, when the output signal of the flip-flop circuit of the preceding stage is converged to a level that is different from a level of the input signal after the metastable state, the flip-flop circuit of the subsequent state cannot sometimes receive the proper input signal at a next system clock after a system clock at which the metastable state occurred. Therefore, when an input signal of plural bits is synchronized with the system clock, a time difference of one system clock cycle occurs between the bits, which may cause a malfunction of a module of a subsequent stage.